As a method for automatic wire routing of a semiconductor integrated circuit, various ones such as a labyrinth search method or a line search method have been reported (e.g. PROCEEDINGS OF THE IEEE, VOL. 71, NO. 1, PP. 328-336, JANUARY 1983). However, as the semiconductor integrated circuit has recently been made large-scale, its wiring area has also been increased or been made of multiple layers and, therefore, to process the entire wiring area of the semiconductor integrated circuit in block according to the foregoing methods has caused the increase of the processing time or of the used memories of the computer making it gradually difficult.
Conventionally, in order to solve this type of problem, the wiring area available on the semiconductor integrated circuit has been divided into a plurality of portions, each of which is processed in block according to the foregoing method. According to this method, as illustrated in FIG. 1 in the form of a flowchart of the conventional system, before the actual wire routing process is carried out, a process S-100 called a schematic wire routing is provided and, after a schematic wiring area is determined based on the library data regarding the wire routing scheme, the aforementioned labyrinth search method or line search method is repeatedly carried out for each divided wiring area according to a process S-102 called a detailed wire routing until the wire routing process of the entire wiring area is completed.
The foregoing process is specifically described with reference to the accompanying drawings. FIG. 2 is a schematic representation of the wiring areas available on a conventional semiconductor integrated circuit, in which each area sectioned in the form of a rectangle indicates a divided wiring area to be processed in block when the detailed wire routing is carried out. As shown, signs A, B, C . . . are each assigned in the direction of column, and signs 1, 2, 3 . . . are each assigned in the direction of row. The divided wiring area corresponding to the intersection of the row and the column is called (A, 1), and the like. If, by way of example, a terminal "a" at the area (A,5) and a terminal "b" at the area (D,2) are interconnected to each other, then, in the schematic wire routing process, it is determined over the entire wiring area which divided area each wire passes through, from which side the wire enters the selected divided wiring area, or from which side it leaves (S-100). With the terminals "a" and "b", it is determined that they are interconnected using, for example, divided wiring areas drawn by oblique lines of FIG. 2, and the wire starting from the terminal "a" passes through the area (A,5) for the right side and enters the area (B,5) from the left side to pass through the right side and enters the area (C,5) from the left side to leave for the upper side. In this determination, it is taken into account to make the wiring density of each divided area as extremely uniform as possible, to make the number of the divided areas each wire passes through as extremely small as possible and to satisfy several preset conditions as much as possible.
Thereafter, in the detailed wire routing process, a wiring scheme down to the boundary side is determined for each divided area. At this time, if the wire routing of the adjacent divided wiring area has already been carried out, then the wire passing through its boundary side is laid so that it is connected to the same wire at the boundary side. On the other hand, if otherwise, then the wire passing through that boundary side is drawn to an arbitrary position on the boundary side so that when the wire routing at the adjacent divided wiring area is carried out it is connected to the same wire at the boundary side (S-102).
In recent years, as typically represented by a computer system called a work station, with the technical progress of the computer suitable for carrying out a concurrent processing under the network environment, or with further increase of the scale of the semiconductor integrated circuit, also in the wire routing process of the semiconductor integrated circuit, a trend has been increased in which the data processing speed is aimed at increasing through the concurrent processing. When the foregoing conventional wire routing process of the semiconductor integrated circuit is adapted to such a concurrent processing, it is considered to use a plurality of computers or calculators and assign the detailed wire routing process for each divided wiring area to each computer or calculator.
However, in the conventional system, when a certain computer or calculator tries to carry out the wire routing at a certain divided area, if the adjacent wiring area is being processed by other computer or calculator, it cannot be determined to which position of a side contacting this adjacent divided wiring area the wire should be drawn. Therefore, until that the wire routing at the adjacent divided wiring areas being processed have been completed, the preceding computer or calculator will have to wait for its own processing.
As described above, in the conventional concurrent wire routing process of the semiconductor integrated circuit, one computer or calculator cannot often help waiting for the completion of the processing by other computer or calculator with the result that it cannot effectively be utilized thus causing the overall processing speed not to be improved.